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EL7156
Data Sheet May 2, 2007 FN7280.3
High Performance Pin Driver
The EL7156 high performance pin driver with three-state is suited to many ATE and level-shifting applications. The 3.5A peak drive capability makes this part an excellent choice when driving high capacitance loads. The output pin OUT is connected to input pins VH or VL respectively, depending on the status of the IN pin. When the OE pin is active low, the output is placed in the three-state mode. The isolation of the output FETs from the power supplies enables VH and VL to be set independently, enabling level-shifting to be implemented. Related to the EL7155, the EL7156 adds a lower supply pin VS- and makes VL an isolated and independent input. This feature adds applications flexibility and improves switching response due to the increased enhancement of the output FETs. This pin driver has improved performance over existing pin drivers. It is specifically designed to operate at voltages down to 0V across the switch elements while maintaining good speed and ON-resistance characteristics. Available in the 8 Ld SOIC and 8 Ld PDIP packages, the EL7156 is specified for operation over the full -40C to +85C temperature range.
Features
* Clocking speeds up to 40MHz * 15ns tR/tFat 2000pF CLOAD * 0.5ns rise and fall times mismatch * 0.5ns tON-tOFF prop delay mismatch * 3.5pF typical input capacitance * 3.5A peak drive * Low ON-resistance of 3.5 * High capacitive drive capability * Operates from 4.5V to 16.5V * Pb-free plus anneal available (RoHS compliant)
Applications
* ATE/burn-in testers * Level shifting * IGBT drivers * CCD drivers
Ordering Information
PART NUMBER EL7156CN EL7156CNZ (Note) EL7156CS PART MARKING EL7156CN EL7156CN Z 7156CS 7156CS 7156CS 7156CSZ 7156CSZ TAPE & REEL 7" 13" 7" 13" PACKAGE 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) PKG. DWG. # MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
Pinout
EL7156 (8 LD PDIP, SOIC) TOP VIEW
VS+ 1 OE 2 IN 3 GND 4 L O G I C 8 VH 7 OUT
EL7156CS-T7
6 VL 5 VS-
EL7156CS-T13 EL7156CSZ (Note) EL7156CSZ-T7 (Note)
EL7156CSZ-T13 7156CSZ (Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL7156
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.3V, VS +0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
Thermal Information
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROVH ROVL IOUT IPK
VS+ = +15V, VH = +15V, VL = 0V, VS- = 0V, TA = +25C, unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Logic `1' Input Voltage Logic `1' Input Current Logic `0' Input Voltage Logic `0' Input Current Input Capacitance Input Resistance VIL = 0V VIH = VS+
2.4 0.1 10 0.8 0.1 3.5 50 10
V A V A pF M
ON-Resistance VH to OUT ON-Resistance VL to OUT Output Leakage Current Peak Output Current (linear resistive operation) Continuous Output Current
IOUT = -200 mA IOUT = +200 mA OE = 0V, OUT = VH/VL Source Sink Source/Sink 200
2.7 3.5 0.1 3.5 3.5
4.5 5.5 10
A A A mA
IDC POWER SUPPLY IS IVH
Power Supply Current Off Leakage at VH and VL
Inputs = VS+ VH, VL = 0V
1.3 4
3 10
mA A
SWITCHING CHARACTERISTICS tR tF tRF td-1 td-2 td td-3 td-4 Rise Time Fall Time tR, tF Mismatch Turn-Off Delay Time Turn-On Delay Time td-1-td-2 Mismatch Three-state Delay Enable Three-state Delay Disable CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF 14.5 15 0.5 9.5 10 0.5 10 10 ns ns ns ns ns ns ns ns
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FN7280.3 May 2, 2007
EL7156
Electrical Specifications
PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROVH ROVL IOUT IPK ON-Resistance VH to OUT ON-Resistance VL to OUT Output Leakage Current Peak Output Current (linear resistive operation) Continuous Output Current IOUT = -200mA IOUT = +200mA OE = 0V, OUT = VH/VL Source Sink Source/Sink 200 3.4 4 0.1 3.5 3.5 5 6 10 A A A mA Logic `1' Input Voltage Logic `1' Input Current Logic `0' Input Voltage Logic `0' Input Current Input Capacitance Input Resistance VIL = 0V 0.1 3.5 50 VIH = VS+ 2.0 0.1 10 0.8 10 V A V A pF M VS+ = +5V, VH = +5V, VL = -5V, VS- = -5V, TA = +25C, unless otherwise specified. (Continued) CONDITION MIN TYP MAX UNIT
DESCRIPTION
IDC POWER SUPPLY IS VH
Power Supply Current Off Leakage at VH and VL
Inputs = VS+ VH, VL = 0V
1 4
2.5 10
mA A
SWITCHING CHARACTERISTICS tR tF tRF td-1 td-2 td td-3 td-4 Rise Time Fall Time tR, tF Mismatch Turn-Off Delay Time Turn-On Delay Time td-1-td-2 Mismatch Three-state Delay Enable Three-state Delay Disable CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF 17 17 0 11.5 12 0.5 10 10 ns ns ns ns ns ns ns ns
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FN7280.3 May 2, 2007
EL7156 Typical Performance Curves
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.0 POWER DISSIPATION (W) PDIP8 0.8 0.6 0.4 JA = 160C/W 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 1.0 5 10 SUPPLY VOLTAGE (V) 15 INPUT VOLTAGE (V) JA = 100C/W 1.6 HYSTERESIS MAX TJ = +125C HIGH THRESHOLD 1.8 T = +25C
SOIC8
1.4
1.2
LOW THRESHOLD
FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. INPUT THRESHOLD vs SUPPLY VOLTAGE
2.0 SUPPLY CURRENT (mA)
T = +25C
6 5 "ON" RESISTANCE () 4 3 2 1 0
IOUT = 200mA, T = +25C, VS+ = VH, VS- = VL = 0V VOUT - VL
1.6
1.2
ALL INPUTS = GND
VOUT - VH
0.8
0.4
ALL INPUTS = VS+
0 5 10 SUPPLY VOLTAGE (V) 15
5
7.5
10
12.5
15
SUPPLY VOLTAGE (V)
FIGURE 3. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. "ON"-RESISTANCE vs SUPPLY VOLTAGE
30
CL = 2000pF, T = +25C
20
CL = 2000pF, VS+ = 15V
18 RISE/FALL TIME (ns) RISE/FALL TIME (ns) 25 tR 20 tI 15 tF tF 16
14 tR 12
10 5 10
tR 15
10 -50
0
50 TEMPERATURE (C)
100
150
SUPPLY VOLTAGE (V)
FIGURE 5. RISE/FALL TIME vs SUPPLY VOLTAGE
FIGURE 6. RISE/FALL TIME vs TEMPERATURE
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FN7280.3 May 2, 2007
EL7156 Typical Performance Curves
17 CL = 2000pF, T = +25C
(Continued)
CL = 2000pF, VS+ = 15V
14
15 DELAY TIME (ns)
DELAY TIME (ns)
td-2
12
td-2
13
10 td-1
11
td-1
8
9 5 10 SUPPLY VOLTAGE (V) 15
6 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
FIGURE 7. PROPAGATION DELAY vs SUPPLY VOLTAGE
FIGURE 8. PROPAGATION DELAY vs TEMPERATURE
70 60 50 40 30 20 10
VS+ = +15V, T = +25C
5
VS+ = VH = 15V, VS- = VL = 0V, T = +25C, f = 20kHz
SUPPLY CURRENT (mA)
4
RISE/FALL TIME (ns)
3
tF
2
tR
1
0 100
1000 LOAD CAPACITANCE (pF)
10000
0 100
1000 LOAD CAPACITANCE (pF)
10000
FIGURE 9. RISE/FALL TIME vs LOAD CAPACITANCE
FIGURE 10. SUPPLY CURRENT vs LOAD CAPACITANCE
14 12 SUPPLY CURRENT (mA) 10 8 6 4 2
VS+ = VH, VS -= VL = 0V, CL = 0pF
30 25
VS+ = VH, VS- = VL = 0V, CL = 0pF
VS+ = VH = 15V
IVH (mA)
VS+ = VH = 10V
20 15 10 5
VS+ = VH = 15V
VS+ = VH = 10V
0 1M
VS+ = S+=VH V VH = 5V 2M 3M 4M 6M 6M 7M 8M 9M 10M
0 1M
VS+ =VS+=VH VH = 5V 2M 3M 4M 6M 6M 7M 8M 9M 10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. SUPPLY CURRENT vs FREQUENCY
FIGURE 12. VH SUPPLY CURRENT vs FREQUENCY
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FN7280.3 May 2, 2007
EL7156 Truth Table
OE 0 0 1 1 IN 0 1 0 1 OUT Three-state Three-state VH VL
Operating Voltage Range
PIN VS- to GND VS+ to VSVH to VL VS+ to VH VS+ to GND VL to VSThree-state Output MIN -5 5 0 0 5 0 VL MAX 0 16.5 16.5 16.5 16.5 16.5 VH
Timing Diagram
5V INPUT 2.5V 0 INVERTED OUTPUT 90% 10% td1 tF td2 tR
Standard Test Configuration
VH VS+ VS+ 4.7F 10k 0.1F OE IN GND 1 2 3 4
EL7156
0.1F 8 L O G I C
4.7F
OUT 7 6 5 0.1F 4.7F VL 2000pF
0.1F 4.7F
VS-
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FN7280.3 May 2, 2007
EL7156 Pin Descriptions
PIN 1 2 NAME VS+ OE FUNCTION Positive Supply Voltage Output Enable
VS+
EQUIVALENT CIRCUIT
INPUT
VSCIRCUIT 1
3 4 5 6 7
IN GND VSVL OUT
Input Ground Negative Supply Voltage Lower Output Voltage Output
Reference Circuit 1
VH
VSVS+ VOUT VSVSVL
CIRCUIT 2
8
VH
High Output Voltage
Block Diagram
OE VH
VS+
IN LEVEL SHIFTER GND
THREESTATE CONTROL
OUT
VSVL
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FN7280.3 May 2, 2007
EL7156 Applications Information
Product Description
The EL7156 is a high performance 40MHz pin driver. It contains two analog switches connecting VH and VL to OUT. Depending on the value of the IN pin, one of the two switches will be closed and the other switch open. An output enable (OE) is also supplied which opens both switches simultaneously. Due to the topology of the EL7156, both the VH and VL pins can be connected to any voltage between the VS+ and VSpins, but VH must be greater than VL in order to prevent turning on the body diode at the output stage. The EL7156 is available in both the 8 Ld SOIC and the 8 Ld PDIP packages. The relevant package should be chosen depending on the calculated power dissipation. Power dissipation may be calculated:
PD = ( V S x I S ) + ( C VS x V S x f ) + [ ( C INT + C L ) x V OUT x f ] (EQ. 1)
2 2
where: VS is the total power supply to the EL7156 (from VS+ to GND) VOUT is the swing on the output (VH to VL) CVS is the integral capacitance due to VS+ CINT is the integral load capacitance due to VH IS is the quiescent supply current (3mA max) f is frequency
TABLE 1. INTEGRAL CAPACITANCE VS+ = VH(V) 5 10 15 CVS(pF) 80 85 90 CINT(pF) 120 145 180
Three-state Operation
When the OE pin is low, the output is three-state (floating). The output voltage is the parasitic capacitance's voltage. It can be any voltage between VH and VL, depending on the previous state. At three-state, the output voltage can be pushed to any voltage between VH and VL. The output voltage can't be pushed higher than VH or lower than VL since the body diode at the output stage will turn on.
Supply Voltage Range and Input Compatibility
The EL7156 is designed for operation on supplies from 5V to 15V (4.5V to 16.5V maximum). "Operating Voltage Range" on page 6 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. All input pins are compatible with both 3V and 5V CMOS signals. With a positive supply (VS+) of 5V, the EL7156 is also compatible with TTL inputs.
Having obtained the application's power dissipation, a maximum package thermal coefficient may be determined, to maintain the internal die temperature below TJMAX:
T JMAX - T MAX JA = ---------------------------------------PD (EQ. 2)
where: TJMAX is the maximum junction temperature (+125C) TMAX is the maximum operating temperature PD is the power dissipation calculated above JA thermal resistance on junction to ambient JA is 160C/W for the SOIC8 package and 100C/W for the PDIP8 package when using a standard JEDEC JESD51-3 single-layer test board. If TJMAX is greater than +125C when calculated using Equation 2, then one of the following actions must be taken: Reduce JA the system by designing more heat-sinking into the PCB (as compared to the standard JEDEC JESD51-3). Use the PDIP8 instead of the SOIC8 package. De-rate the application either by reducing the switching frequency, the capacitive load, or the maximum operating (ambient) temperature (TMAX).
Power Supply Bypassing
When using the EL7156, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7156 necessitate the use of a bypass capacitor between the supplies (VS+ and VS-) and GND pins. It is recommended that a 2.2F tantalum capacitor be used in parallel with a 0.1F low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7156 is driving highly capacitive loads.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the EL7156 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation, die temperature must be kept below TJMAX (+125C). It is necessary to calculate the power dissipation for a given application prior to selecting the package type.
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FN7280.3 May 2, 2007
EL7156 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. C 2/07 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN7280.3 May 2, 2007
EL7156 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7280.3 May 2, 2007

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